`ifndef UDLY
`define UDLY 1
`endif
module mem_mux__9(
  mem_req__0__valid,
  mem_req__0__ready,
  mem_req__0__we_n,
  mem_req__0__addr,
  mem_req__0__rdata,
  mem_req__0__wdata,
  mem__0__ce_n,
  mem__0__we_n,
  mem__0__addr,
  mem__0__rdata,
  mem__0__wdata,
  mem__1__ce_n,
  mem__1__we_n,
  mem__1__addr,
  mem__1__rdata,
  mem__1__wdata,
  mem__2__ce_n,
  mem__2__we_n,
  mem__2__addr,
  mem__2__rdata,
  mem__2__wdata,
  mem__3__ce_n,
  mem__3__we_n,
  mem__3__addr,
  mem__3__rdata,
  mem__3__wdata,
  clk,
  rstn
);
//parameter declare
//port declare
input mem_req__0__valid;
output mem_req__0__ready;
input mem_req__0__we_n;
input [31:0] mem_req__0__addr;
output [63:0] mem_req__0__rdata;
input [63:0] mem_req__0__wdata;
output mem__0__ce_n;
output mem__0__we_n;
output [31:0] mem__0__addr;
input [63:0] mem__0__rdata;
output [63:0] mem__0__wdata;
output mem__1__ce_n;
output mem__1__we_n;
output [31:0] mem__1__addr;
input [63:0] mem__1__rdata;
output [63:0] mem__1__wdata;
output mem__2__ce_n;
output mem__2__we_n;
output [31:0] mem__2__addr;
input [63:0] mem__2__rdata;
output [63:0] mem__2__wdata;
output mem__3__ce_n;
output mem__3__we_n;
output [31:0] mem__3__addr;
input [63:0] mem__3__rdata;
output [63:0] mem__3__wdata;
input clk;
input rstn;
//channel declare
//wire declare
logic __mem_sel_835;
logic __mem_sel_836;
logic __mem_sel_837;
logic __mem_sel_838;
logic [2:0] __mem_sel_idx_839;
logic __mem_sel_841;
logic __mem_sel_842;
logic __mem_sel_843;
logic __mem_sel_844;
logic [2:0] __mem_sel_idx_845;
logic __mem_sel_847;
logic __mem_sel_848;
logic __mem_sel_849;
logic __mem_sel_850;
logic [2:0] __mem_sel_idx_851;
logic __mem_sel_853;
logic __mem_sel_854;
logic __mem_sel_855;
logic __mem_sel_856;
logic [2:0] __mem_sel_idx_857;
logic __mux2req_ready_860;
logic __t_861;
logic __t_862;
logic __t_863;
logic __t_864;
logic [1:0] __ret_866;
logic [1:0] __index_867;
logic [1:0] __index_868;
logic [1:0] __index_869;
logic [1:0] __index_870;
logic __valid_871;
logic __cond_872;
logic __cond_873;
logic __cond_874;
logic __cond_875;
logic __valid_876;
logic __cond_877;
logic __cond_878;
logic __cond_879;
logic __cond_880;
logic __valid_881;
logic __cond_882;
logic __cond_883;
logic __cond_884;
logic __cond_885;
logic __valid_886;
logic __cond_887;
logic __cond_888;
logic __cond_889;
logic __cond_890;
logic [1:0] __ret_892;
logic [1:0] __index_893;
logic [1:0] __index_894;
logic [1:0] __index_895;
logic [1:0] __index_896;
logic __valid_897;
logic __cond_898;
logic __cond_899;
logic __cond_900;
logic __cond_901;
logic __valid_902;
logic __cond_903;
logic __cond_904;
logic __cond_905;
logic __cond_906;
logic __valid_907;
logic __cond_908;
logic __cond_909;
logic __cond_910;
logic __cond_911;
logic __valid_912;
logic __cond_913;
logic __cond_914;
logic __cond_915;
logic __cond_916;
logic [1:0] __ret_918;
logic [1:0] __index_919;
logic [1:0] __index_920;
logic [1:0] __index_921;
logic [1:0] __index_922;
logic __valid_923;
logic __cond_924;
logic __cond_925;
logic __cond_926;
logic __cond_927;
logic __valid_928;
logic __cond_929;
logic __cond_930;
logic __cond_931;
logic __cond_932;
logic __valid_933;
logic __cond_934;
logic __cond_935;
logic __cond_936;
logic __cond_937;
logic __valid_938;
logic __cond_939;
logic __cond_940;
logic __cond_941;
logic __cond_942;
logic [1:0] __ret_944;
logic [1:0] __index_945;
logic [1:0] __index_946;
logic [1:0] __index_947;
logic [1:0] __index_948;
logic __valid_949;
logic __cond_950;
logic __cond_951;
logic __cond_952;
logic __cond_953;
logic __valid_954;
logic __cond_955;
logic __cond_956;
logic __cond_957;
logic __cond_958;
logic __valid_959;
logic __cond_960;
logic __cond_961;
logic __cond_962;
logic __cond_963;
logic __valid_964;
logic __cond_965;
logic __cond_966;
logic __cond_967;
logic __cond_968;
logic __cond_969;
logic __cond_970;
logic __cond_971;
logic __cond_972;
logic [31:0] __addr_t_973;
logic __cond_974;
logic [31:0] __mem_addr_t_975;
logic __cond_976;
logic __cond_977;
logic [31:0] __addr_t_978;
logic __cond_979;
logic [31:0] __mem_addr_t_980;
logic __cond_981;
logic __cond_982;
logic [31:0] __addr_t_983;
logic __cond_984;
logic [31:0] __mem_addr_t_985;
logic __cond_986;
logic __cond_987;
logic [31:0] __addr_t_988;
logic __cond_989;
logic [31:0] __mem_addr_t_990;
logic __cond_991;
logic __cond_992;
//port wire declare
wire mem_req__0__valid;
logic mem_req__0__ready;
wire mem_req__0__we_n;
wire [31:0] mem_req__0__addr;
logic [63:0] mem_req__0__rdata;
wire [63:0] mem_req__0__wdata;
logic mem__0__ce_n;
logic mem__0__we_n;
logic [31:0] mem__0__addr;
wire [63:0] mem__0__rdata;
logic [63:0] mem__0__wdata;
logic mem__1__ce_n;
logic mem__1__we_n;
logic [31:0] mem__1__addr;
wire [63:0] mem__1__rdata;
logic [63:0] mem__1__wdata;
logic mem__2__ce_n;
logic mem__2__we_n;
logic [31:0] mem__2__addr;
wire [63:0] mem__2__rdata;
logic [63:0] mem__2__wdata;
logic mem__3__ce_n;
logic mem__3__we_n;
logic [31:0] mem__3__addr;
wire [63:0] mem__3__rdata;
logic [63:0] mem__3__wdata;
wire clk;
wire rstn;
//register declare
//register init and update
reg [2:0] __mem_sel_idx_dly_840;
wire [2:0] ___mem_sel_idx_dly_840;
always @(posedge clk or negedge rstn) begin
  if(!rstn) begin
    __mem_sel_idx_dly_840 <= #`UDLY 3'h0;
  end
  else begin
    __mem_sel_idx_dly_840 <= #`UDLY ___mem_sel_idx_dly_840;
  end
end

reg [2:0] __mem_sel_idx_dly_846;
wire [2:0] ___mem_sel_idx_dly_846;
always @(posedge clk or negedge rstn) begin
  if(!rstn) begin
    __mem_sel_idx_dly_846 <= #`UDLY 3'h0;
  end
  else begin
    __mem_sel_idx_dly_846 <= #`UDLY ___mem_sel_idx_dly_846;
  end
end

reg [2:0] __mem_sel_idx_dly_852;
wire [2:0] ___mem_sel_idx_dly_852;
always @(posedge clk or negedge rstn) begin
  if(!rstn) begin
    __mem_sel_idx_dly_852 <= #`UDLY 3'h0;
  end
  else begin
    __mem_sel_idx_dly_852 <= #`UDLY ___mem_sel_idx_dly_852;
  end
end

reg [2:0] __mem_sel_idx_dly_858;
wire [2:0] ___mem_sel_idx_dly_858;
always @(posedge clk or negedge rstn) begin
  if(!rstn) begin
    __mem_sel_idx_dly_858 <= #`UDLY 3'h0;
  end
  else begin
    __mem_sel_idx_dly_858 <= #`UDLY ___mem_sel_idx_dly_858;
  end
end

reg __mux2req_ready_dly_859;
wire ___mux2req_ready_dly_859;
always @(posedge clk or negedge rstn) begin
  if(!rstn) begin
    __mux2req_ready_dly_859 <= #`UDLY 1'h0;
  end
  else begin
    __mux2req_ready_dly_859 <= #`UDLY ___mux2req_ready_dly_859;
  end
end

reg [1:0] __round_865;
wire [1:0] ___round_865;
always @(posedge clk or negedge rstn) begin
  if(!rstn) begin
    __round_865 <= #`UDLY 2'h0;
  end
  else begin
    __round_865 <= #`UDLY ___round_865;
  end
end

reg [1:0] __round_891;
wire [1:0] ___round_891;
always @(posedge clk or negedge rstn) begin
  if(!rstn) begin
    __round_891 <= #`UDLY 2'h0;
  end
  else begin
    __round_891 <= #`UDLY ___round_891;
  end
end

reg [1:0] __round_917;
wire [1:0] ___round_917;
always @(posedge clk or negedge rstn) begin
  if(!rstn) begin
    __round_917 <= #`UDLY 2'h0;
  end
  else begin
    __round_917 <= #`UDLY ___round_917;
  end
end

reg [1:0] __round_943;
wire [1:0] ___round_943;
always @(posedge clk or negedge rstn) begin
  if(!rstn) begin
    __round_943 <= #`UDLY 2'h0;
  end
  else begin
    __round_943 <= #`UDLY ___round_943;
  end
end

//assign logic
assign __t_861 /* 64 */ = ((0<=mem_req__0__addr)&&(mem_req__0__addr<255) /* 434 */ ) /* 64 */ ;
assign __mem_sel_835 /* 65 */ = (__t_861 /* 66 */ )?(mem_req__0__valid /* 67 */ ):1'b0 /* 69 */  /* 68 */ ;
assign __t_862 /* 64 */ = ((256<=mem_req__0__addr)&&(mem_req__0__addr<511) /* 434 */ ) /* 64 */ ;
assign __mem_sel_841 /* 65 */ = (__t_862 /* 66 */ )?(mem_req__0__valid /* 67 */ ):1'b0 /* 69 */  /* 68 */ ;
assign __t_863 /* 64 */ = ((512<=mem_req__0__addr)&&(mem_req__0__addr<767) /* 434 */ ) /* 64 */ ;
assign __mem_sel_847 /* 65 */ = (__t_863 /* 66 */ )?(mem_req__0__valid /* 67 */ ):1'b0 /* 69 */  /* 68 */ ;
assign __t_864 /* 64 */ = ((768<=mem_req__0__addr)&&(mem_req__0__addr<1023) /* 434 */ ) /* 64 */ ;
assign __mem_sel_853 /* 65 */ = (__t_864 /* 66 */ )?(mem_req__0__valid /* 67 */ ):1'b0 /* 69 */  /* 68 */ ;
assign ___round_865 /* 330 */ = (1'b1 /* 331 */ )?((__ret_866==4-1 /* 332 */ )?(0 /* 332 */ ):__ret_866+1 /* 333 */  /* 333 */ ):__round_865 /* 335 */  /* 334 */ ;
assign __index_867 /* 337 */ = __round_865 /* 337 */ ;
assign __index_868 /* 339 */ = ((__round_865+1)>=4 /* 340 */ )?(__round_865+1-4 /* 341 */ ):__round_865+1 /* 343 */  /* 342 */ ;
assign __index_869 /* 339 */ = ((__round_865+2)>=4 /* 340 */ )?(__round_865+2-4 /* 341 */ ):__round_865+2 /* 343 */  /* 342 */ ;
assign __index_870 /* 339 */ = ((__round_865+3)>=4 /* 340 */ )?(__round_865+3-4 /* 341 */ ):__round_865+3 /* 343 */  /* 342 */ ;
assign __cond_872 /* 242 */ = 0==__index_867 /* 242 */ ;
assign __cond_873 /* 242 */ = 1==__index_867 /* 242 */ ;
assign __cond_874 /* 242 */ = 2==__index_867 /* 242 */ ;
assign __cond_875 /* 242 */ = 3==__index_867 /* 242 */ ;
assign __valid_871 /* 346 */ = ((((({ 1{__cond_872} }&((__mem_sel_835 /* 312 */ ))) /* 244 */ )|({ 1{__cond_873} }&((__mem_sel_836 /* 312 */ ))) /* 246 */ )|({ 1{__cond_874} }&((__mem_sel_837 /* 312 */ ))) /* 246 */ )|({ 1{__cond_875} }&((__mem_sel_838 /* 312 */ ))) /* 246 */ ) /* 346 */ ;
assign __cond_877 /* 242 */ = 0==__index_868 /* 242 */ ;
assign __cond_878 /* 242 */ = 1==__index_868 /* 242 */ ;
assign __cond_879 /* 242 */ = 2==__index_868 /* 242 */ ;
assign __cond_880 /* 242 */ = 3==__index_868 /* 242 */ ;
assign __valid_876 /* 346 */ = ((((({ 1{__cond_877} }&((__mem_sel_835 /* 312 */ ))) /* 244 */ )|({ 1{__cond_878} }&((__mem_sel_836 /* 312 */ ))) /* 246 */ )|({ 1{__cond_879} }&((__mem_sel_837 /* 312 */ ))) /* 246 */ )|({ 1{__cond_880} }&((__mem_sel_838 /* 312 */ ))) /* 246 */ ) /* 346 */ ;
assign __cond_882 /* 242 */ = 0==__index_869 /* 242 */ ;
assign __cond_883 /* 242 */ = 1==__index_869 /* 242 */ ;
assign __cond_884 /* 242 */ = 2==__index_869 /* 242 */ ;
assign __cond_885 /* 242 */ = 3==__index_869 /* 242 */ ;
assign __valid_881 /* 346 */ = ((((({ 1{__cond_882} }&((__mem_sel_835 /* 312 */ ))) /* 244 */ )|({ 1{__cond_883} }&((__mem_sel_836 /* 312 */ ))) /* 246 */ )|({ 1{__cond_884} }&((__mem_sel_837 /* 312 */ ))) /* 246 */ )|({ 1{__cond_885} }&((__mem_sel_838 /* 312 */ ))) /* 246 */ ) /* 346 */ ;
assign __cond_887 /* 242 */ = 0==__index_870 /* 242 */ ;
assign __cond_888 /* 242 */ = 1==__index_870 /* 242 */ ;
assign __cond_889 /* 242 */ = 2==__index_870 /* 242 */ ;
assign __cond_890 /* 242 */ = 3==__index_870 /* 242 */ ;
assign __valid_886 /* 346 */ = ((((({ 1{__cond_887} }&((__mem_sel_835 /* 312 */ ))) /* 244 */ )|({ 1{__cond_888} }&((__mem_sel_836 /* 312 */ ))) /* 246 */ )|({ 1{__cond_889} }&((__mem_sel_837 /* 312 */ ))) /* 246 */ )|({ 1{__cond_890} }&((__mem_sel_838 /* 312 */ ))) /* 246 */ ) /* 346 */ ;
assign __ret_866 /* 349 */ = (__valid_871 /* 215 */ )?(__index_867 /* 216 */ ):(__valid_876 /* 215 */ )?(__index_868 /* 216 */ ):(__valid_881 /* 215 */ )?(__index_869 /* 216 */ ):(__valid_886 /* 215 */ )?(__index_870 /* 216 */ ):(4 /* 213 */ ) /* 218 */  /* 217 */  /* 217 */  /* 217 */  /* 217 */ ;
assign __mem_sel_idx_839 /* 80 */ = (__ret_866 /* 350 */ ) /* 80 */ ;
assign ___mem_sel_idx_dly_840 /* 81 */ = __mem_sel_idx_839 /* 81 */ ;
assign ___round_891 /* 330 */ = (1'b1 /* 331 */ )?((__ret_892==4-1 /* 332 */ )?(0 /* 332 */ ):__ret_892+1 /* 333 */  /* 333 */ ):__round_891 /* 335 */  /* 334 */ ;
assign __index_893 /* 337 */ = __round_891 /* 337 */ ;
assign __index_894 /* 339 */ = ((__round_891+1)>=4 /* 340 */ )?(__round_891+1-4 /* 341 */ ):__round_891+1 /* 343 */  /* 342 */ ;
assign __index_895 /* 339 */ = ((__round_891+2)>=4 /* 340 */ )?(__round_891+2-4 /* 341 */ ):__round_891+2 /* 343 */  /* 342 */ ;
assign __index_896 /* 339 */ = ((__round_891+3)>=4 /* 340 */ )?(__round_891+3-4 /* 341 */ ):__round_891+3 /* 343 */  /* 342 */ ;
assign __cond_898 /* 242 */ = 0==__index_893 /* 242 */ ;
assign __cond_899 /* 242 */ = 1==__index_893 /* 242 */ ;
assign __cond_900 /* 242 */ = 2==__index_893 /* 242 */ ;
assign __cond_901 /* 242 */ = 3==__index_893 /* 242 */ ;
assign __valid_897 /* 346 */ = ((((({ 1{__cond_898} }&((__mem_sel_841 /* 312 */ ))) /* 244 */ )|({ 1{__cond_899} }&((__mem_sel_842 /* 312 */ ))) /* 246 */ )|({ 1{__cond_900} }&((__mem_sel_843 /* 312 */ ))) /* 246 */ )|({ 1{__cond_901} }&((__mem_sel_844 /* 312 */ ))) /* 246 */ ) /* 346 */ ;
assign __cond_903 /* 242 */ = 0==__index_894 /* 242 */ ;
assign __cond_904 /* 242 */ = 1==__index_894 /* 242 */ ;
assign __cond_905 /* 242 */ = 2==__index_894 /* 242 */ ;
assign __cond_906 /* 242 */ = 3==__index_894 /* 242 */ ;
assign __valid_902 /* 346 */ = ((((({ 1{__cond_903} }&((__mem_sel_841 /* 312 */ ))) /* 244 */ )|({ 1{__cond_904} }&((__mem_sel_842 /* 312 */ ))) /* 246 */ )|({ 1{__cond_905} }&((__mem_sel_843 /* 312 */ ))) /* 246 */ )|({ 1{__cond_906} }&((__mem_sel_844 /* 312 */ ))) /* 246 */ ) /* 346 */ ;
assign __cond_908 /* 242 */ = 0==__index_895 /* 242 */ ;
assign __cond_909 /* 242 */ = 1==__index_895 /* 242 */ ;
assign __cond_910 /* 242 */ = 2==__index_895 /* 242 */ ;
assign __cond_911 /* 242 */ = 3==__index_895 /* 242 */ ;
assign __valid_907 /* 346 */ = ((((({ 1{__cond_908} }&((__mem_sel_841 /* 312 */ ))) /* 244 */ )|({ 1{__cond_909} }&((__mem_sel_842 /* 312 */ ))) /* 246 */ )|({ 1{__cond_910} }&((__mem_sel_843 /* 312 */ ))) /* 246 */ )|({ 1{__cond_911} }&((__mem_sel_844 /* 312 */ ))) /* 246 */ ) /* 346 */ ;
assign __cond_913 /* 242 */ = 0==__index_896 /* 242 */ ;
assign __cond_914 /* 242 */ = 1==__index_896 /* 242 */ ;
assign __cond_915 /* 242 */ = 2==__index_896 /* 242 */ ;
assign __cond_916 /* 242 */ = 3==__index_896 /* 242 */ ;
assign __valid_912 /* 346 */ = ((((({ 1{__cond_913} }&((__mem_sel_841 /* 312 */ ))) /* 244 */ )|({ 1{__cond_914} }&((__mem_sel_842 /* 312 */ ))) /* 246 */ )|({ 1{__cond_915} }&((__mem_sel_843 /* 312 */ ))) /* 246 */ )|({ 1{__cond_916} }&((__mem_sel_844 /* 312 */ ))) /* 246 */ ) /* 346 */ ;
assign __ret_892 /* 349 */ = (__valid_897 /* 215 */ )?(__index_893 /* 216 */ ):(__valid_902 /* 215 */ )?(__index_894 /* 216 */ ):(__valid_907 /* 215 */ )?(__index_895 /* 216 */ ):(__valid_912 /* 215 */ )?(__index_896 /* 216 */ ):(4 /* 213 */ ) /* 218 */  /* 217 */  /* 217 */  /* 217 */  /* 217 */ ;
assign __mem_sel_idx_845 /* 80 */ = (__ret_892 /* 350 */ ) /* 80 */ ;
assign ___mem_sel_idx_dly_846 /* 81 */ = __mem_sel_idx_845 /* 81 */ ;
assign ___round_917 /* 330 */ = (1'b1 /* 331 */ )?((__ret_918==4-1 /* 332 */ )?(0 /* 332 */ ):__ret_918+1 /* 333 */  /* 333 */ ):__round_917 /* 335 */  /* 334 */ ;
assign __index_919 /* 337 */ = __round_917 /* 337 */ ;
assign __index_920 /* 339 */ = ((__round_917+1)>=4 /* 340 */ )?(__round_917+1-4 /* 341 */ ):__round_917+1 /* 343 */  /* 342 */ ;
assign __index_921 /* 339 */ = ((__round_917+2)>=4 /* 340 */ )?(__round_917+2-4 /* 341 */ ):__round_917+2 /* 343 */  /* 342 */ ;
assign __index_922 /* 339 */ = ((__round_917+3)>=4 /* 340 */ )?(__round_917+3-4 /* 341 */ ):__round_917+3 /* 343 */  /* 342 */ ;
assign __cond_924 /* 242 */ = 0==__index_919 /* 242 */ ;
assign __cond_925 /* 242 */ = 1==__index_919 /* 242 */ ;
assign __cond_926 /* 242 */ = 2==__index_919 /* 242 */ ;
assign __cond_927 /* 242 */ = 3==__index_919 /* 242 */ ;
assign __valid_923 /* 346 */ = ((((({ 1{__cond_924} }&((__mem_sel_847 /* 312 */ ))) /* 244 */ )|({ 1{__cond_925} }&((__mem_sel_848 /* 312 */ ))) /* 246 */ )|({ 1{__cond_926} }&((__mem_sel_849 /* 312 */ ))) /* 246 */ )|({ 1{__cond_927} }&((__mem_sel_850 /* 312 */ ))) /* 246 */ ) /* 346 */ ;
assign __cond_929 /* 242 */ = 0==__index_920 /* 242 */ ;
assign __cond_930 /* 242 */ = 1==__index_920 /* 242 */ ;
assign __cond_931 /* 242 */ = 2==__index_920 /* 242 */ ;
assign __cond_932 /* 242 */ = 3==__index_920 /* 242 */ ;
assign __valid_928 /* 346 */ = ((((({ 1{__cond_929} }&((__mem_sel_847 /* 312 */ ))) /* 244 */ )|({ 1{__cond_930} }&((__mem_sel_848 /* 312 */ ))) /* 246 */ )|({ 1{__cond_931} }&((__mem_sel_849 /* 312 */ ))) /* 246 */ )|({ 1{__cond_932} }&((__mem_sel_850 /* 312 */ ))) /* 246 */ ) /* 346 */ ;
assign __cond_934 /* 242 */ = 0==__index_921 /* 242 */ ;
assign __cond_935 /* 242 */ = 1==__index_921 /* 242 */ ;
assign __cond_936 /* 242 */ = 2==__index_921 /* 242 */ ;
assign __cond_937 /* 242 */ = 3==__index_921 /* 242 */ ;
assign __valid_933 /* 346 */ = ((((({ 1{__cond_934} }&((__mem_sel_847 /* 312 */ ))) /* 244 */ )|({ 1{__cond_935} }&((__mem_sel_848 /* 312 */ ))) /* 246 */ )|({ 1{__cond_936} }&((__mem_sel_849 /* 312 */ ))) /* 246 */ )|({ 1{__cond_937} }&((__mem_sel_850 /* 312 */ ))) /* 246 */ ) /* 346 */ ;
assign __cond_939 /* 242 */ = 0==__index_922 /* 242 */ ;
assign __cond_940 /* 242 */ = 1==__index_922 /* 242 */ ;
assign __cond_941 /* 242 */ = 2==__index_922 /* 242 */ ;
assign __cond_942 /* 242 */ = 3==__index_922 /* 242 */ ;
assign __valid_938 /* 346 */ = ((((({ 1{__cond_939} }&((__mem_sel_847 /* 312 */ ))) /* 244 */ )|({ 1{__cond_940} }&((__mem_sel_848 /* 312 */ ))) /* 246 */ )|({ 1{__cond_941} }&((__mem_sel_849 /* 312 */ ))) /* 246 */ )|({ 1{__cond_942} }&((__mem_sel_850 /* 312 */ ))) /* 246 */ ) /* 346 */ ;
assign __ret_918 /* 349 */ = (__valid_923 /* 215 */ )?(__index_919 /* 216 */ ):(__valid_928 /* 215 */ )?(__index_920 /* 216 */ ):(__valid_933 /* 215 */ )?(__index_921 /* 216 */ ):(__valid_938 /* 215 */ )?(__index_922 /* 216 */ ):(4 /* 213 */ ) /* 218 */  /* 217 */  /* 217 */  /* 217 */  /* 217 */ ;
assign __mem_sel_idx_851 /* 80 */ = (__ret_918 /* 350 */ ) /* 80 */ ;
assign ___mem_sel_idx_dly_852 /* 81 */ = __mem_sel_idx_851 /* 81 */ ;
assign ___round_943 /* 330 */ = (1'b1 /* 331 */ )?((__ret_944==4-1 /* 332 */ )?(0 /* 332 */ ):__ret_944+1 /* 333 */  /* 333 */ ):__round_943 /* 335 */  /* 334 */ ;
assign __index_945 /* 337 */ = __round_943 /* 337 */ ;
assign __index_946 /* 339 */ = ((__round_943+1)>=4 /* 340 */ )?(__round_943+1-4 /* 341 */ ):__round_943+1 /* 343 */  /* 342 */ ;
assign __index_947 /* 339 */ = ((__round_943+2)>=4 /* 340 */ )?(__round_943+2-4 /* 341 */ ):__round_943+2 /* 343 */  /* 342 */ ;
assign __index_948 /* 339 */ = ((__round_943+3)>=4 /* 340 */ )?(__round_943+3-4 /* 341 */ ):__round_943+3 /* 343 */  /* 342 */ ;
assign __cond_950 /* 242 */ = 0==__index_945 /* 242 */ ;
assign __cond_951 /* 242 */ = 1==__index_945 /* 242 */ ;
assign __cond_952 /* 242 */ = 2==__index_945 /* 242 */ ;
assign __cond_953 /* 242 */ = 3==__index_945 /* 242 */ ;
assign __valid_949 /* 346 */ = ((((({ 1{__cond_950} }&((__mem_sel_853 /* 312 */ ))) /* 244 */ )|({ 1{__cond_951} }&((__mem_sel_854 /* 312 */ ))) /* 246 */ )|({ 1{__cond_952} }&((__mem_sel_855 /* 312 */ ))) /* 246 */ )|({ 1{__cond_953} }&((__mem_sel_856 /* 312 */ ))) /* 246 */ ) /* 346 */ ;
assign __cond_955 /* 242 */ = 0==__index_946 /* 242 */ ;
assign __cond_956 /* 242 */ = 1==__index_946 /* 242 */ ;
assign __cond_957 /* 242 */ = 2==__index_946 /* 242 */ ;
assign __cond_958 /* 242 */ = 3==__index_946 /* 242 */ ;
assign __valid_954 /* 346 */ = ((((({ 1{__cond_955} }&((__mem_sel_853 /* 312 */ ))) /* 244 */ )|({ 1{__cond_956} }&((__mem_sel_854 /* 312 */ ))) /* 246 */ )|({ 1{__cond_957} }&((__mem_sel_855 /* 312 */ ))) /* 246 */ )|({ 1{__cond_958} }&((__mem_sel_856 /* 312 */ ))) /* 246 */ ) /* 346 */ ;
assign __cond_960 /* 242 */ = 0==__index_947 /* 242 */ ;
assign __cond_961 /* 242 */ = 1==__index_947 /* 242 */ ;
assign __cond_962 /* 242 */ = 2==__index_947 /* 242 */ ;
assign __cond_963 /* 242 */ = 3==__index_947 /* 242 */ ;
assign __valid_959 /* 346 */ = ((((({ 1{__cond_960} }&((__mem_sel_853 /* 312 */ ))) /* 244 */ )|({ 1{__cond_961} }&((__mem_sel_854 /* 312 */ ))) /* 246 */ )|({ 1{__cond_962} }&((__mem_sel_855 /* 312 */ ))) /* 246 */ )|({ 1{__cond_963} }&((__mem_sel_856 /* 312 */ ))) /* 246 */ ) /* 346 */ ;
assign __cond_965 /* 242 */ = 0==__index_948 /* 242 */ ;
assign __cond_966 /* 242 */ = 1==__index_948 /* 242 */ ;
assign __cond_967 /* 242 */ = 2==__index_948 /* 242 */ ;
assign __cond_968 /* 242 */ = 3==__index_948 /* 242 */ ;
assign __valid_964 /* 346 */ = ((((({ 1{__cond_965} }&((__mem_sel_853 /* 312 */ ))) /* 244 */ )|({ 1{__cond_966} }&((__mem_sel_854 /* 312 */ ))) /* 246 */ )|({ 1{__cond_967} }&((__mem_sel_855 /* 312 */ ))) /* 246 */ )|({ 1{__cond_968} }&((__mem_sel_856 /* 312 */ ))) /* 246 */ ) /* 346 */ ;
assign __ret_944 /* 349 */ = (__valid_949 /* 215 */ )?(__index_945 /* 216 */ ):(__valid_954 /* 215 */ )?(__index_946 /* 216 */ ):(__valid_959 /* 215 */ )?(__index_947 /* 216 */ ):(__valid_964 /* 215 */ )?(__index_948 /* 216 */ ):(4 /* 213 */ ) /* 218 */  /* 217 */  /* 217 */  /* 217 */  /* 217 */ ;
assign __mem_sel_idx_857 /* 80 */ = (__ret_944 /* 350 */ ) /* 80 */ ;
assign ___mem_sel_idx_dly_858 /* 81 */ = __mem_sel_idx_857 /* 81 */ ;
assign __mux2req_ready_860 /* 89 */ = (__mem_sel_idx_839==0 /* 215 */ )?((1'b1 /* 86 */ ) /* 216 */ ):(__mem_sel_idx_845==0 /* 215 */ )?((1'b1 /* 86 */ ) /* 216 */ ):(__mem_sel_idx_851==0 /* 215 */ )?((1'b1 /* 86 */ ) /* 216 */ ):(__mem_sel_idx_857==0 /* 215 */ )?((1'b1 /* 86 */ ) /* 216 */ ):((0 /* 88 */ ) /* 213 */ ) /* 218 */  /* 217 */  /* 217 */  /* 217 */  /* 217 */ ;
assign __cond_969 /* 242 */ = __mem_sel_idx_dly_840==0 /* 242 */ ;
assign __cond_970 /* 242 */ = __mem_sel_idx_dly_846==0 /* 242 */ ;
assign __cond_971 /* 242 */ = __mem_sel_idx_dly_852==0 /* 242 */ ;
assign __cond_972 /* 242 */ = __mem_sel_idx_dly_858==0 /* 242 */ ;
assign mem_req__0__rdata /* 90 */ = ((((({ 64{__cond_969} }&((mem__0__rdata /* 87 */ ))) /* 244 */ )|({ 64{__cond_970} }&((mem__1__rdata /* 87 */ ))) /* 246 */ )|({ 64{__cond_971} }&((mem__2__rdata /* 87 */ ))) /* 246 */ )|({ 64{__cond_972} }&((mem__3__rdata /* 87 */ ))) /* 246 */ ) /* 90 */ ;
assign ___mux2req_ready_dly_859 /* 93 */ = __mux2req_ready_860 /* 93 */ ;
assign mem_req__0__ready /* 94 */ = __mux2req_ready_860 /* 94 */ ;
assign __cond_974 /* 242 */ = (__mem_sel_idx_839==0)&&__mem_sel_835 /* 242 */ ;
assign __addr_t_973 /* 111 */ = (({ 32{__cond_974} }&(((mem_req__0__addr) /* 109 */ ))) /* 244 */ ) /* 111 */ ;
assign __mem_addr_t_975 /* 112 */ = __addr_t_973-0 /* 112 */ ;
assign mem__0__addr /* 113 */ = __mem_addr_t_975[31:0] /* 113 */ ;
assign __cond_976 /* 242 */ = (__mem_sel_idx_839==0)&&__mem_sel_835 /* 242 */ ;
assign mem__0__wdata /* 114 */ = (({ 64{__cond_976} }&((mem_req__0__wdata /* 108 */ ))) /* 244 */ ) /* 114 */ ;
assign __cond_977 /* 242 */ = (__mem_sel_idx_839==0)&&__mem_sel_835 /* 242 */ ;
assign mem__0__we_n /* 115 */ = (({ 1{__cond_977} }&((mem_req__0__we_n /* 106 */ ))) /* 244 */ ) /* 115 */ ;
assign mem__0__ce_n /* 116 */ = ((__mem_sel_idx_839==0)&&__mem_sel_835 /* 215 */ )?(((!mem_req__0__valid) /* 107 */ ) /* 216 */ ):((1'b1 /* 110 */ ) /* 213 */ ) /* 218 */  /* 217 */ ;
assign __cond_979 /* 242 */ = (__mem_sel_idx_845==0)&&__mem_sel_841 /* 242 */ ;
assign __addr_t_978 /* 111 */ = (({ 32{__cond_979} }&(((mem_req__0__addr) /* 109 */ ))) /* 244 */ ) /* 111 */ ;
assign __mem_addr_t_980 /* 112 */ = __addr_t_978-256 /* 112 */ ;
assign mem__1__addr /* 113 */ = __mem_addr_t_980[31:0] /* 113 */ ;
assign __cond_981 /* 242 */ = (__mem_sel_idx_845==0)&&__mem_sel_841 /* 242 */ ;
assign mem__1__wdata /* 114 */ = (({ 64{__cond_981} }&((mem_req__0__wdata /* 108 */ ))) /* 244 */ ) /* 114 */ ;
assign __cond_982 /* 242 */ = (__mem_sel_idx_845==0)&&__mem_sel_841 /* 242 */ ;
assign mem__1__we_n /* 115 */ = (({ 1{__cond_982} }&((mem_req__0__we_n /* 106 */ ))) /* 244 */ ) /* 115 */ ;
assign mem__1__ce_n /* 116 */ = ((__mem_sel_idx_845==0)&&__mem_sel_841 /* 215 */ )?(((!mem_req__0__valid) /* 107 */ ) /* 216 */ ):((1'b1 /* 110 */ ) /* 213 */ ) /* 218 */  /* 217 */ ;
assign __cond_984 /* 242 */ = (__mem_sel_idx_851==0)&&__mem_sel_847 /* 242 */ ;
assign __addr_t_983 /* 111 */ = (({ 32{__cond_984} }&(((mem_req__0__addr) /* 109 */ ))) /* 244 */ ) /* 111 */ ;
assign __mem_addr_t_985 /* 112 */ = __addr_t_983-512 /* 112 */ ;
assign mem__2__addr /* 113 */ = __mem_addr_t_985[31:0] /* 113 */ ;
assign __cond_986 /* 242 */ = (__mem_sel_idx_851==0)&&__mem_sel_847 /* 242 */ ;
assign mem__2__wdata /* 114 */ = (({ 64{__cond_986} }&((mem_req__0__wdata /* 108 */ ))) /* 244 */ ) /* 114 */ ;
assign __cond_987 /* 242 */ = (__mem_sel_idx_851==0)&&__mem_sel_847 /* 242 */ ;
assign mem__2__we_n /* 115 */ = (({ 1{__cond_987} }&((mem_req__0__we_n /* 106 */ ))) /* 244 */ ) /* 115 */ ;
assign mem__2__ce_n /* 116 */ = ((__mem_sel_idx_851==0)&&__mem_sel_847 /* 215 */ )?(((!mem_req__0__valid) /* 107 */ ) /* 216 */ ):((1'b1 /* 110 */ ) /* 213 */ ) /* 218 */  /* 217 */ ;
assign __cond_989 /* 242 */ = (__mem_sel_idx_857==0)&&__mem_sel_853 /* 242 */ ;
assign __addr_t_988 /* 111 */ = (({ 32{__cond_989} }&(((mem_req__0__addr) /* 109 */ ))) /* 244 */ ) /* 111 */ ;
assign __mem_addr_t_990 /* 112 */ = __addr_t_988-768 /* 112 */ ;
assign mem__3__addr /* 113 */ = __mem_addr_t_990[31:0] /* 113 */ ;
assign __cond_991 /* 242 */ = (__mem_sel_idx_857==0)&&__mem_sel_853 /* 242 */ ;
assign mem__3__wdata /* 114 */ = (({ 64{__cond_991} }&((mem_req__0__wdata /* 108 */ ))) /* 244 */ ) /* 114 */ ;
assign __cond_992 /* 242 */ = (__mem_sel_idx_857==0)&&__mem_sel_853 /* 242 */ ;
assign mem__3__we_n /* 115 */ = (({ 1{__cond_992} }&((mem_req__0__we_n /* 106 */ ))) /* 244 */ ) /* 115 */ ;
assign mem__3__ce_n /* 116 */ = ((__mem_sel_idx_857==0)&&__mem_sel_853 /* 215 */ )?(((!mem_req__0__valid) /* 107 */ ) /* 216 */ ):((1'b1 /* 110 */ ) /* 213 */ ) /* 218 */  /* 217 */ ;
//cell instance
endmodule
